Ideally, in a properly fabricated semiconductor wafer, all of the integrated circuits would be functional. In reality, the number of functional devices may range from close to 100% to only a few good circuits per wafer.
Thus, when a device fails to function as it should, it is desirable to determine the cause of failure. By understanding failure mechanisms of nonfunctional devices, corrections may be made to eliminate or decrease the causes of these failures. Decreasing failures in subsequently fabricated devices results in increased wafer yield.
Specifically, if a failure occurs in a memory cell in the memory array of a memory device, it is preferable if electrical tests on that individual cell can be performed to determine its failure mode. Traditionally, memory devices have been designed such that individual memory cells are not directly accessible from the external input/output terminals of the chip. Very often, peripheral input/output circuitry, such as input (write) and output (read) data drivers, are located in the path between the cell and external terminals. This makes characterization of individual memory cells virtually impossible.
As will be seen, the present invention overcomes this problem by incorporating test circuitry directly into the memory device itself. This test circuitry functions to disable the peripheral I/O circuitry and to select and enable the section of the array in which the single cell is located so that electrical characterization can be performed. Consequently, the present invention enables testing of individual cells directly through the input/output terminals of the chip. Therefore, by providing a means for testing single cells, further knowledge of the cell's failure mechanisms is provided and device yield may be optimized.